1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for electrostatic discharge (ESD) protection.
2. Description of the Related Art
A metal oxide semiconductor field effect transistor (MOSFET) is a device which is very effective against electrostatic discharge. The MOSFET provides a discharge path for a large current between a source and a drain due to a parasitic bipolar transistor turned on during an ESD event, thereby protecting a circuit from a large external signal.
ESD protection for the MOSFET is based on a snap-back mechanism and will be described below with reference to FIGS. 1A and 1B. FIG. 1A is a sectional view of an N-channel MOSFET (NMOSFET) formed on a semiconductor substrate. If a strong electric field is generated by intersecting a drain junction 110, an avalanche breakdown is caused by the electric field in a depletion layer extended to both sides of the drain junction 110, and thus electric charges occur. Some of the electric charges flow into the drain, and remaining electric charges flow into the substrate. A local voltage for forward-biasing a source junction 120 occurs between the source and the substrate of the NMOSFET due to an accumulation of the electric charges flowing into the substrate, and when the local voltage exceeds about 0.6V, the parasitic bipolar transistor Q is turned on, thereby discharging an ESD current into a drain of the NMOSFET. Here, reference numeral R denotes substrate resistance. FIG. 1B is a graph illustrating the relationship between current and voltage for the NMOSFET during an ESD event. Here, Vt and Vsp denote a break-down voltage and a snap-back voltage (about 0.6V), respectively.
The above-mentioned NMOSFET for ESD protection may have a multi-fingered structure so as to handle a large ESD current. In particular, an NMOSFET having a long gate must be used in an input/output (I/O) interface block because of parasitic resistance, inductance, and capacitance existing in a cable for connecting a board on which a package and a chip are mounted, a chip, and an external system to one another. Moreover, an NMOSFET having the multi-fingered structure is used to realize the NMOSFET in a predetermined area more effectively.
FIG. 2A is a plan view of a conventional NMOSFET having the multi-fingered structure. A P well region 210 is formed on a semiconductor substrate (not shown), and a plurality of gate electrodes G1, G2, G3, and G4 are formed on the semiconductor substrate on which the P well region 210 is formed, and N+ source regions S1, S2, and S3 and drain regions D1 and D2 are formed on right and left sides of each of the gate electrodes G1, G2, G3, and G4. A P+ diffusion region 220 for supplying a bias to the P well region 210 is formed around the outside of the P well region 210. FIG. 2B is a sectional view of a semiconductor substrate 200 of FIG. 2A taken along line 2B-2Bxe2x80x2 of FIG. 2A. Parasitic bipolar transistors Q1, Q2, Q3, and Q4 operating between source regions S1, S2, and S3, drain regions D1 and D2, the P well region 210 and the P+ diffusion region 220 are conceptually shown in FIG. 2B. Each source and drain of the NMOSFET functions as an emitter and a collector of the parasitic bipolar transistor, and a large current is discharged between the emitter and the collector of the parasitic bipolar transistor during an ESD event, thereby protecting an internal circuit. A reference numeral Rsub denotes substrate resistance existing between a base and the P+ diffusion region 220 of the parasitic bipolar transistor.
However, when the NMOSFETs having the multi-fingered structure are used for ESD protection, it is important that the NMOSFETs be turned on simultaneously. A reason why the MOSFETs are not turned on simultaneously in these prior art devices will be described with reference to FIG. 3. FIG. 3 partially illustrates the NMOSFET of FIG. 2B and the parasitic bipolar transistor of the NMOSFET. As shown in FIG. 3, since distances from the P30  diffusion region 220 to the parasitic bipolar transistors Q1 and Q2 are different, substrate resistance, that is, values of base resistors R1 and R2, are different. As a result, the local voltage, which occurs on the source junction of each NMOSFET due to accumulation of the electric charges after the avalanche break down, changes. Thus, the time required for each of the parasitic bipolar transistors to reach the snap-back voltage is different, and thus the parasitic bipolar transistors are turned on at different times. In FIG. 3, the parasitic bipolar transistor Q2 having large base resistance is turned on faster than the parasitic bipolar transistor Q1.
Non-simultaneous turn-ons of the NMOSFETs having the multi-fingered structure causes serious problems for the discharge characteristics of the NMOSFET having a silicide layer, which is formed on the source and drain regions of each transistor so as to guarantee high-speed operation of the transistor by increasing a saturation current of the transistor and by reducing the parasitic resistance and capacitance. This will be described with reference to FIG. 4A. FIG. 4A is a sectional view of a transistor having the multi-fingered structure formed on a semiconductor substrate 300. A silicide layer 340 is formed on a gate electrode 310 on a gate oxide layer 370 and on source and drain regions 320 and 330 of the transistor by a selfaligned silicide (SALICIDE) process. In view of ESD, resistance of the parasitic bipolar transistor is reduced by the suicide layer 340 during an ESD event after snapback. This is referred to as xe2x80x9conxe2x80x9d resistance Ron and denotes the inverse number of the slope of a current-voltage graph after reaching a snap-back voltage Vsp in the current-voltage graph of FIG.1 B. A discharged current is increased by reducing the xe2x80x9conxe2x80x9d resistance, and electric charges accumulate on source and drain junctions (region marked by a dotted line) adjacent to the silicide layer 340 around sidewalls 350 of the gate electrode 310, thereby resulting in high current density in the source and drain junctions. As mentioned previously, the NMOSFETs having relatively high base resistance for NMOSFETs having the multi-fingered structure are turned on faster than other NMOSFETs, and a predetermined interval of time is necessary to turn on the neighboring NMOSFETs. However, the source and drain junctions are destroyed because of the high current density caused by the silicide layer, and thus it is difficult to allow for the predetermined interval of time to turn on the NMOSFETs. As a result, only some NMOSFETs are discharged, and thus benefits to using NMOSFETs having the multi-fingered structure are negated.
As one method for solving these problems, a suicide layer 340xe2x80x2 of source and drain regions 320 and 330 is formed at a predetermined interval W1 from gate electrode sidewalls 350, thereby dispersing the current density of the junction, as shown in FIG. 4B. However, the method has other problems. First, a separate mask (not shown) is required to the source and drain regions 320 and 330 regions for selective formation of the silicide layer, thus complicating the process. Second, it is difficult to perform a high-speed operation due to an increase in parasitic resistance of the source and drain regions 320 and 330. Also, in a case where the SALICIDE process for the source and drain regions 320 and 330 is performed simultaneously with the SALICIDE process of the gate electrode 340, it is difficult to obtain a process margin for formation of the mask (not shown).
Meanwhile, as another method for solving these problems, a discharge area can be increased by increasing the area of source and drain junctions 380, as shown in FIG. 4C. However, in this method, performance of the transistor due to the increase in parasitic resistance deteriorates, and there are limitations to an increase in the discharge area, and thus the change in ESD characteristics is small. As described above, unexplained reference numerals in FIGS. 4B and 4C denote the same elements as those in FIG. 4A, and the descriptions thereof will be omitted.
To solve the above problems, it is an objective of the present invention to provide a semiconductor device for ESD protection capable of improving discharge efficiency by increasing xe2x80x9conxe2x80x9d resistance of a MOSFET having a multi-fingered structure.
Accordingly, there is provided in accordance with the invention a semiconductor device for ESD protection. The semiconductor device for ESD protection includes a plurality of transistors having a multi-fingered structure, a plurality of multilayer interconnections separated from one another, formed in proportion to the number of common drain regions of the transistors, and connected to the common drain regions of each of the transistors, a pad conductive layer formed on the multilayer interconnections, and a plurality of contact plugs for connecting interconnections of the multilayer interconnections to one another and for connecting the multilayer interconnections to the pad conductive layer so that a current flowing the common drain regions of the transistors may pass only through the multilayer interconnections connected to the common drain regions and may flow into the pad conductive layer.
In one embodiment, the multilayer interconnections are formed of Al, Cu, or an alloy of Al and Cu, and the pad conductive layer is formed of Al, Cu, or an alloy of Al and Cu.
It is preferable that the gate electrodes and source/drain regions of the transistors include silicide formed by a self-aligned silicide (SALICIDE) process, and the silicide is one of cobalt silicide and tungsten silicide.
It is preferable that the number of the multilayer interconnections is the same as the number of common drain regions of the transistors having the multi-fingered structure.
According to an embodiment of the present invention, interconnections of each layer forming the multilayer interconnections may have a stripe pattern. Also, according to another embodiment of the present invention, the multilayer interconnections may include sequentially stacked first and second interconnection layers comprising interconnections that are isolated island-shaped patterns in each layer forming the multilayer interconnections, and the first and second interconnection layers may be connected to the plurality of contact plugs so that current flowing the interconnections may pass through the plurality of isolated islandshaped patterns of the first and second interconnection layers and may flow into the pad conductive layer.